A 70GOPS, 34mW Multi-Carrier MIMO Chip in 3.5mm/sup ~/

D. Markovic, R. Brodersen, B. Nikolic
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.  
An ASIC realization of the MIMO baseband processing for a multi-antenna WLAN is described. The chip implements a 4×4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1GOPS/mW in just 3.5mm 2 in a 90nm CMOS. The computational throughput of 70GOPS is implemented with 0.5M gates at a 100MHz clock and 385mV supply, dissipating 34mW of power. With optimal channel conditions the algorithm implemented can deliver up to 250Mbps over 16MHz band.
doi:10.1109/vlsic.2006.1705358 fatcat:pgfrzvvswje2fmrlxntvabulhm