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In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs
2019
Micromachines
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM
doi:10.3390/mi10020124
pmid:30769837
pmcid:PMC6412702
fatcat:3w5j76nfp5eo7a6e3ztbouuntm