There are three main approaches to the architecture of the convolver : the data flow approach which is inspired from systolic concept and the data flow for matrix-matrix multiplication pioneered by Kung and Leiserson; the multiplieraccumulator (MAC) structures and the bit-plane approach. These architectures are reviewed in the thesis. It is also well known that convolution is very similar to the multiplication process. They are, however, not identical. In this thesis subtle differences between

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... ultiplication and convolution are pointed out and it is shown that with proper care convolution can be carried out by normal multiplication operation with its overlap-add and overlap-save techniques for long sequences in the time domain just as DFT's overlap-add, overlap-save techniques in the frequency domain. Based on the similarities between multiplication and convolution a new serial convolver architecture is presented which can be programmed to function as a serial multiplier or as a serial convolver. It is further shown that this serial architecture can be modified to provide IIR computation, matrix-vector and matrix-matrix multiplications in single chip with lesser penalty in area and chip pins than its parallel counterpart. A VLSI implementation of a 4-bit wordlength by 4 taps convolver is also presented.