A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor

Luis A. Tarazona, Doug A. Edwards, Luis A. Plana
<span title="">2009</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/6nxn3oxzcveorfagbcbilem2ay" style="color: black;">2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools</a> </i> &nbsp;
The implementation of an efficient result forwarding unit for asynchronous processors faces the problem of the inherent lack of synchronisation between result producer and consumer units. An efficient, full-custom solution to this problem has been proposed and implemented before (in the AMULET3 asynchronous processor) with the consequent limitations on design-space exploration and technology portability. The use of automatic synthesis to describe asynchronous systems is attractive in terms of
more &raquo; ... pid development, technology mapping transparency and design space exploration. This paper presents the description of a synthesisable result forwarding unit for an asynchronous microprocessor, using the syntax-directed synthesis approach and targeting a robust quasi-delay-insensitive implementation. The description of such a system also serves as a complex case study to evaluate the capabilities and limitations of syntax-directed synthesis when used as a tool to automate the synthesis of performancedemanding asynchronous systems.
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dsd.2009.163">doi:10.1109/dsd.2009.163</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dsd/TarazonaEP09.html">dblp:conf/dsd/TarazonaEP09</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/oskuicnsi5ctfexsdq7q64oqry">fatcat:oskuicnsi5ctfexsdq7q64oqry</a> </span>
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