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SMT-based verification of parameterized systems
2016
Proceedings of the 2016 24th ACM SIGSOFT International Symposium on Foundations of Software Engineering - FSE 2016
It is well known that verification of safety properties of sequential programs is reducible to satisfiability modulo theory of a first-order logic formula, called a verification condition (VC). The reduction is used both in deductive and automated verification, the difference is only in whether the user or the solver provides candidates for inductive invariants. In this paper, we extend the reduction to parameterized systems consisting of arbitrary many copies of a user-specified process, and
doi:10.1145/2950290.2950330
dblp:conf/sigsoft/GurfinkelSM16
fatcat:5wgwysestzcxvgqkguekrdigsa