Test-architecture optimization and test scheduling for SOCs with core-level expansion of compressed test patterns

Anders Larsson, Erik Larsson, Krishnendu Chakrabarty, Petru Eles, Zebo Peng
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
1 The ever-increasing test data volume for core-based systemon-chip (SOC) integrated circuits is resulting in high test times and excessive tester memory requirements. To reduce both test time and test data volume, we propose a technique for test-architecture optimization and test scheduling that is based on core-level expansion of compressed test patterns. For each wrapped embedded core and its decompressor, we show that the test time does not decrease monotonically with the width of test
more » ... s mechanism (TAM) at the decompressor input. We optimize the wrapper and decompressor designs for each core, as well as the TAM architecture and the test schedule at the SOC level. Experimental results for SOCs crafted from several industrial cores demonstrate that the proposed method leads to significant reduction in test data volume and test time, especially when compared to a method that does not rely on core-level decompression of patterns.
doi:10.1145/1403375.1403422 fatcat:7um4ryku4zcrvck4iwrbirmmci