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Proceedings of the conference on Design, automation and test in Europe - DATE '08
1 The ever-increasing test data volume for core-based systemon-chip (SOC) integrated circuits is resulting in high test times and excessive tester memory requirements. To reduce both test time and test data volume, we propose a technique for test-architecture optimization and test scheduling that is based on core-level expansion of compressed test patterns. For each wrapped embedded core and its decompressor, we show that the test time does not decrease monotonically with the width of testdoi:10.1145/1403375.1403422 fatcat:7um4ryku4zcrvck4iwrbirmmci