A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS

A. V. Rylyakov, J. A. Tierno, D. Z. Turker, J.-O. Plouchart, H. A. Ainspan, D. Friedman
2008 Digest of technical papers / IEEE International Solid-State Circuits Conference  
doi:10.1109/isscc.2008.4523284 dblp:conf/isscc/RylyakovTTPAF08 fatcat:nx4okbosafaczgye7y7xvfum5y