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Efficient Sequential Architecture of AES CCM for the IEEE 802.16e
IEICE transactions on information and systems
In this paper, we propose efficient sequential AES CCM architecture for the IEEE 802.16e. In the proposed architecture, only one AES encryption core is used and the operation of the CTR and the CBC-MAC is processed concurrently within one round. With this design approach, we can design sequential AES CCM architecture having 570 Mbps@102.4 MHz throughput and 1,397 slices at a Spartan3 3s5000 device. key words: cryptography, communication system security, integrated chip design, FPGAdoi:10.1587/transinf.e95.d.185 fatcat:d7vaqmbcmnhxlmcfjytxm6hrpu