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Ultra low-cost defect protection for microprocessor pipelines
2006
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems - ASPLOS-XII
The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Silicon failure mechanisms, such as transistor wearout and manufacturing defects, are a growing challenge that threatens the yield and product lifetime of future systems. In this paper we introduce the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system
doi:10.1145/1168857.1168868
dblp:conf/asplos/ShyamCPBA06
fatcat:hcqq4pai5ngjni6rbi4nukad3m