Simulating the impact of pattern-dependent poly-CD variation on circuit performance

B.E. Stine, D.S. Boning, J.E. Chung, D.J. Ciplickas, J.K. Kibarian
1998 IEEE transactions on semiconductor manufacturing  
In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 m 64 2 2 2 8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell.
doi:10.1109/66.728551 fatcat:bqgf3h4x3rdjljt6gkew4mqyjq