[Front matter]

2021 2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)  
Moore's law continues to drive the advancements of density, power, and performance for SOCs (e.g., CPU, GPU, FPGA, ASIC/ASSP) via transistor feature size and interconnect shrinkage, as well as switch speed increases. In the near future, transistors and semiconductors will enter the atomic size: Angstrom (Å). Meanwhile, Moore's law continues to drive the SERDES I/O speed doubling at a pace around every 3 years, and soon will reach 224 Gbps per lane speed. In this talk, we will review the SERDES
more » ... /O speed advancement path and highlight the end-to-end challenges at 224 Gbps, from silicon, to package, to PCB/connectors, and associated solution options. Furthermore, we will discuss how Moore's law and atomic Angstrom process nodes will enable 224 Gbps data rate to achieve the desired power, performance, and density via More-Moore, and More-than-Moore. Biography: Dr. Peng (Mike) Li is an Intel Fellow and the technologist for high-speed I/O and interconnects at Intel Corporation. He serves as Intel's technical expert and adviser in high-speed I/O and link technology; standards; SerDes architecture; electrical and optical signaling and interconnects; silicon photonics integration; optical field-programmable gate arrays (OFPGAs); and high-speed simulation, debug and test for jitter, noise, signaling and power integrity, from deign validation to high-volume manufacturing (HVM). Li joined Intel in 2015 with the acquisition of Altera Corp., where he had held a similar role since 2012. Before joining Altera in 2007, Li spent nearly a decade at Wavecrest Corp. culminating in his seven-year tenure as chief technology officer (CTO). He began his career in 1991 as a postdoctorate researcher on high-energy astrophysics at the Space Sciences Laboratory at the
doi:10.1109/epeps51341.2021.9609191 fatcat:odhavj7d6jegbgcxvnploex6rq