Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A Tutorial

Bryan Casper, Frank O'Mahony
2009 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
The performance of high-speed wireline data links depend crucially on the quality and precision of their clocking infrastructure. For future applications, such as microprocessor systems that require terabytes/s of aggregate bandwidth, signaling system designers will have to become even more aware of detailed clock design tradeoffs in order to jointly optimize I/O power, bandwidth, reliability, silicon area and testability. The goal of this tutorial is to assist I/O circuit and system designers
more » ... n developing intuitive and practical understanding of I/O clocking tradeoffs at all levels of the link hierarchy from the circuit-level implementation to system-level architecture. Index Terms-Clock distribution, clock recovery, high-speed I/O, phase-locked loops.
doi:10.1109/tcsi.2008.931647 fatcat:m2zj3kalbvad7ee5m2znin4t7u