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RT-level ITC'99 benchmarks and first ATPG results
2000
IEEE Design & Test of Computers
Effective high-level ATPG tools are increasingly needed, as an essential element in the quest for reducing as much as possible the designer work on gate-level descriptions. We propose a new set of benchmark circuits targeted to researchers working in the area of RT-level automatic test sequence generation. The developed benchmarks share the characteristics of typical synthesizable blocks, are available as both RTL VHDL descriptions and gate level netlists, and allow the evaluation of the
doi:10.1109/54.867894
fatcat:m7al3e3xnneo3egscjhj75iquu