RT-level ITC'99 benchmarks and first ATPG results

F. Corno, M.S. Reorda, G. Squillero
2000 IEEE Design & Test of Computers  
Effective high-level ATPG tools are increasingly needed, as an essential element in the quest for reducing as much as possible the designer work on gate-level descriptions. We propose a new set of benchmark circuits targeted to researchers working in the area of RT-level automatic test sequence generation. The developed benchmarks share the characteristics of typical synthesizable blocks, are available as both RTL VHDL descriptions and gate level netlists, and allow the evaluation of the
more » ... of test sequences generated from RT-level descriptions in terms of attained coverage of gate-level stuck-at faults. Exploiting these benchmarks, we analyzed the effectiveness of a prototypical ATPG tool (called ARTIST) suitable to generate test sequences starting from synthesizable RT-level VHDL descriptions. ARTIST overcomes several limitations inherent with previously proposed approaches, especially in terms of accepted descriptions and level of automation. Also, ARTIST was extremely useful in eliminating some bugs in the benchmarks. The results gathered on the new benchmark suite show that this ATPG was able to generate sequences whose quality is comparable with those generated by a state-of-the-art gate-level ATPG, thus showing the feasibility of RT-level test pattern generation. RTlevel ATPGs will make it feasible for designers to evaluate the testability of their circuits before the synthesis step is performed, and to reduce the cost of the gate-level ATPG step.
doi:10.1109/54.867894 fatcat:m7al3e3xnneo3egscjhj75iquu