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2011 IEEE International Conference on Information and Automation
It is very advantageous to use virtual techniques for testing and developing new hardware and software systems within a manufacturing system. It is, however, of greatest importance that the virtual model can be trusted so that the results of the development and tests can be directly transferred to a real system without any manual last minute changes. In order to trust the result, formal verification techniques can be applied and by doing that guaranteeing a correct system behavior. Today, there<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/icinfa.2011.5949114">doi:10.1109/icinfa.2011.5949114</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/qkqj2e4ydvh3xi2pdonvzqaxvy">fatcat:qkqj2e4ydvh3xi2pdonvzqaxvy</a> </span>
more »... is a gap between how systems are modeled in simulation softwares and formal verification softwares and it is therefore hard to perform formal verification. In order to limit the risk of introducing errors it is also important that the specifications created in the simulation softwares are not manually converted into formal languages. The present paper presents a method for sharing information between the different virtual development tools and formal verification tools. A database, storing necessary control information for verification and controller synthesis, is presented.
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