A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2004; you can also visit <a rel="external noopener" href="http://www.itee.uq.edu.au:80/~bergmann/Research/Online%20Publications/spie.alee.pdf">the original URL</a>. The file type is <code>application/pdf</code>.
Microelectronics: Design, Technology, and Packaging
On-chip communication architectures can have a great influence on the speed and area of System-on-Chip designs, and this influence is expected to be even more pronounced on reconfigurable System-on-Chip (rSoC) designs. To date, little research has been conducted on the performance implications of different on-chip communication architectures for rSoC designs. This paper motivates the need for such research and analyses current and proposed interconnect technologies for rSoC design. The paper<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1117/12.523334">doi:10.1117/12.523334</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ywworo2ipvfgbggssxuedgj33q">fatcat:ywworo2ipvfgbggssxuedgj33q</a> </span>
more »... o describes work in progress on implementation of a simple serial bus and a packet-switched network, as well as a methodology for quantitatively evaluating the performance of these interconnection structures in comparison to conventional buses. Keywords: FPGAs, Reconfigurable Logic, System-on-Chip integrators to convert from the VCI interface to their particular industry standard bus. Similar work is also being carried out in a separate project within our group at University of Queensland  . This projects aims to develop an interface logic generation methodology which can be used across different communications architectures (not just parallel buses). "COMMUNICATION BASED" ARCHITECTURES The silicon industry is moving towards sub 0.1 micron technology in 2004  allowing complex and larger SoCs. As the size of the chip grows relative to the size of the IP cores, on-chip buses will become relatively slow  . Larger chip sizes will also allow several complex processing units to exist in a single system, pushing the on-chip communication to exhibit a multi-processor network behavior. Thus another direction for SoC interconnection network research favours communication based architectures, borrowing ideas from the telecommunications and computer network areas. A brief description of the OSI reference model will be presented below, followed by a look at current developments in this field.
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