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Architecture of a Novel Configurable Communication Processor for SDR
2015
International Journal of VLSI Design & Communication Systems
The design of high performance Digital Signal Processing (DSP) Processors for Software Defined Radio (SDR) with high degree of flexibility and low power consumption has been a major challenge to the scientific community ever since its conception. The basic philosophy of SDR is to implement different modulation or demodulation schemes on the same underlying hardware. Currently available high performance DSP processors, optimized with 'Very Large Instruction Word (VLIW)' architecture and multiply
doi:10.5121/vlsic.2015.6404
fatcat:j2h6izdrcvgmppk5xcdzumskxy