Architecture of a Novel Configurable Communication Processor for SDR

Amiya Karmakar, Amitabha Sinha, Pratik Kumar Sinha, Pijush Biswas
2015 International Journal of VLSI Design & Communication Systems  
The design of high performance Digital Signal Processing (DSP) Processors for Software Defined Radio (SDR) with high degree of flexibility and low power consumption has been a major challenge to the scientific community ever since its conception. The basic philosophy of SDR is to implement different modulation or demodulation schemes on the same underlying hardware. Currently available high performance DSP processors, optimized with 'Very Large Instruction Word (VLIW)' architecture and multiply
more » ... and accumulate (MAC) units, are unable to meet the near real time speed requirements of Software Defined Radios (SDR) due to their inherent sequential execution of compute intensive signal processing algorithms. Moreover, their power dissipation is considerably high. Even though, Application Specific Integrated Circuits (ASIC) exhibit high performance, they are also not suitable because of their lack of flexibility. Various references on FPGA based implementations of reconfigurable architectures for SDRs are also available. However, the Look-up Table (LUT) based implementations of FPGAs are not optimum and therefore, cannot offer highest performance at low silicon cost. Keeping this view, this paper presents the design of a configurable communication processor for Software Defined Radio. The proposed scheme features the performance of an ASIC based design combined with the flexibility of software. Experimental results reveal that the proposed architecture has minimum hardware requirement, improved silicon area utilization and low power dissipation.
doi:10.5121/vlsic.2015.6404 fatcat:j2h6izdrcvgmppk5xcdzumskxy