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Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder
2008 IEEE International Symposium on Circuits and Systems
This paper proposes a novel on-chip interconnection network adapted to a flexible multiprocessor LDPC/turbo decoder and based on the de Bruijn network. The main characteristics of this network -including its logarithmic diameter, scalable aggregate bandwidth, and optimized routing technique-allow it to efficiently support the communicationintensive nature of the two decoding techniques. We present a detailed hardware implementation of the routers and the network interfaces as well as the packetdoi:10.1109/iscas.2008.4541363 dblp:conf/iscas/MoussaBJ08 fatcat:iyj26aymargtznrhu4vopn5ugq