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This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and physical optimizations without incurring unmanageable runtime complexity. Unlike previous approaches to this problem which limit the types of operations and/or architectural features, we take advantage of many architectural characteristics of modern FPGA devices, and utilize many types of optimizations including celldoi:10.1145/968280.968296 dblp:conf/fpga/SuarisLDC04 fatcat:haf7g23yxjex5iogzffalc6tne