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Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
2002
Proceedings - Design Automation Conference
Preserved Fulltext
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet processing circuits on this platform are implemented as Dynamic Hardware Plugin (DHP) modules that fit within a specific region of an FPGA device. The PARBIT tool has been developed to transform and restructure bitfiles created by standard computer aided design tools into partial bitsteams that program DHPs. The
doi:10.1145/514005.514007
fatcat:klgsrkotmvdubjyqkfioyntcma