A 200-MHz 64-bit Dual-Issue CMOS Microprocessor
Daniel W. Dobberpuhl, Richard T. Witek, Randy L. Allmon, Robert Anglin, David Bertucci, Sharon M. Britton, Linda Chao, Robert A. Conrad, Daniel E. Dever, Bruce Gieseke, Soha Hassoun, Gregory W. Hoeppner
(+11 others)
1992
Digital technical journal of Digital Equipment Corporation
A reduced instruction set computer (RISC)-style microprocessor has been designed and tested that operates up to 200 megahertz (MHz). The chip implements a new 64-bit architecture, designed to provide a huge linear address space and to be devoid of bottlenecks that would impede highly concurrent implementations. Fully pipelined and capable of issuing two instructions per clock cycle, this implementation can execute up to 400 million operations per second. The chip includes an 8-kilobyte (KB)
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... he, 8KB D-cache and two associated translation buffers, a four-entry, 32-byte-per-entry write buffer, a pipelined 64-bit integer execution unit with a 32-entry register file, and a pipelined floating-point unit (FPU) with an additional 32 registers. The pin interface includes integral support for an external secondary cache. The package is a 431-pin pin grid array (PGA) with 140 pins dedicated to V(DD)/V(SS) (power supply voltage/ground). The chip is fabricated in a 0.75-micrometer (m) n-well complementary metal-oxide semiconductor (CMOS) process with three layers of metalization. The die measures 16.8 millimeters (mm) x 13.9 mm and contains 1.68 million transistors. Power dissipation is 30 watts (W) from a 3.3-volt (V) supply at 200 MHz. CMOS Process Technology The chip is fabricated in a 0.75-m, 3.3-V, n-well CMOS process optimized for high-performance microprocessor design. Process characteristics are shown in Table 1 . The thin gate oxide and short transistor lengths result in the fast transistors required to operate at 200 MHz. There are no explicit bipolar devices in the process as the incremental process complexity and cost were deemed too large in comparison to the benefits provided -principally more area-efficient large drivers such as clock and I/O. The metal structure is designed to support the high operating frequency of the chip. Metal 3 is very thick and has a relatively large pitch. It is important at these speeds to have a low-resistance metal layer available for power and clock distribution. It is also used for a small set of special signal wires such as the data buses to the pins and the control wires for the two shifters. Metal 1 and metal 2 are maintained at close to their maximum thickness by planarization and by filling metal 1 and metal 2 contacts with tungsten plugs. This removes a potential weak spot in the electromigration characteristics of the process and allows more freedom in the design without compromising reliability.
dblp:journals/dtj/DobberpuhlWAABBCCDGHHKLLMMMMPRSS92
fatcat:7stblq65tzabfajo3o443uuygy
