Scalable compile-time scheduler for multi-core architectures

M. Pelcat, P. Menuet, S. Aridhi, J.-F. Nezan
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing interest. This scheduling consists of statically distributing the tasks that constitute an application between available cores in a multi-core architecture in order to minimize the final latency. This problem has been proven to be NP-complete. A static scheduling algorithm is usually described as a monolithic process,
more » ... and carries out two distinct functionalities: choosing the core to execute a specific function and evaluating the cost of the generated solutions. This paper describes a scheduling module which splits these functionalities into two sub-modules. This division produces an advanced scalability in terms of schedule quality and computation time, and also separates the heuristic complexity from the architecture model precision. Overview and objectives of the scheduler 978-3-9810801-5-5/DATE09
doi:10.1109/date.2009.5090909 dblp:conf/date/PelcatMAN09 fatcat:arsway5zobcmdngj4aoiqsh3jq