WCET-aware register allocation based on graph coloring

Heiko Falk
2009 Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09  
Current compilers lack precise timing models guiding their built-in optimizations. Hence, compilers apply ad-hoc heuristics during optimization to improve code quality. One of the most important optimizations is register allocation. Many compilers heuristically decide when and where to spill a register to memory, without having a clear understanding of the impact of such spill code on a program's run time. This paper extends a graph coloring register allocator such that it uses precise
more » ... e execution time (WCET) models. Using this WCET timing data, the compiler tries to avoid spill code generation along the critical path defining a program's WCET. To the best of our knowledge, this paper is the first one to present a WCET-aware register allocator. Our results underline the effectiveness of the proposed techniques. For a total of 46 realistic benchmarks, we reduced WCETs by 31.2% on average. Additionally, the runtimes of our WCET-aware register allocator still remain acceptable.
doi:10.1145/1629911.1630100 dblp:conf/dac/Falk09 fatcat:odwkc545u5cptnab5a4z3vgxai