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DataScalar architectures
1997
Proceedings of the 24th annual international symposium on Computer architecture - ISCA '97
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory. The program data set (and/or text) is distributed across these memories. In this execution model, each processor broadcasts operands it loads from its local memory to all other units. In this paper, we describe the benefits, costs, and problems associated with the DataScalar model. We also present simulation results
doi:10.1145/264107.264215
dblp:conf/isca/BurgerKG97
fatcat:uqpa6bqnoneopjamcnstnmp3fi