In this paper, a frequency doubler circuit is presented that converts a 0.6 GHz signal to a 1.2 GHz output using standard CMOS 0.18 µm technology. The proposed circuit uses a time-delay element and an XOR logic gate to perform the frequency multiplication and is implemented entirely on-chip. Advantages of this topology include good fundamental suppression, compact layout, and low power consumption. Experimental results show a relatively constant output power of approximately 4 dBm with an input

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... power from -3 dBm to 10 dBm, fundamental and third order harmonic suppressions of up to -30 dBc and a power consumption of 9 mW. The phase noise of the output signal is -117 dBc at a 500 kHz offset. Index Terms -CMOS frequency doubler, multiplier, mixer, frequency conversion.