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The Tag Filter Architecture: An energy-efficient cache and directory design
2017
Journal of Parallel and Distributed Computing
Power consumption in current high-performance chip multiprocessors (CMPs) has become a major design concern that aggravates with the current trend of increasing the core count. A significant fraction of the total power budget is consumed by on-chip caches which are usually deployed with a high associativity degree (even L1 caches are being implemented with eight ways) to enhance the system performance. On a cache access, each way in the corresponding set is accessed in parallel, which is costly
doi:10.1016/j.jpdc.2016.04.016
fatcat:6eeu7a3bvbhu5mjh4himb26bjy