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Code Positioning for VLIW Architectures
[chapter]
2001
Lecture Notes in Computer Science
Several studies have considered reducing instruction cache misses and branch penalty stall cycles by means of various forms of code placement. Most proposed approaches rearrange procedures or basic blocks in order to speed up execution on sequential architectures with branch prediction. Moreover, most works focus mainly on instruction cache performance and disregard execution cycles. To the best of our knowledge, no work has specifically addressed statically scheduled ILP machines like VLIWs,
doi:10.1007/3-540-48228-8_34
fatcat:sja4pkru6jc3xcu3ecxfnk5rei