Multifunction Residue Architectures for Cryptography

Dimitrios Schinianakis, Thanos Stouraitis
<span title="">2014</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/l6r6h4xpzvh6jkuzrx565pgwgu" style="color: black;">IEEE Transactions on Circuits and Systems Part 1: Regular Papers</a> </i> &nbsp;
A design methodology for incorporating Residue Number System (RNS) and Polynomial Residue Number System (PRNS) in Montgomery modular multiplication in or respectively, as well as a VLSI architecture of a dual-field residue arithmetic Montgomery multiplier are presented in this paper. An analysis of input/output conversions to/from residue representation, along with the proposed residue Montgomery multiplication algorithm, reveals common multiply-accumulate data paths both between the converters
more &raquo; ... and between the two residue representations. A versatile architecture is derived that supports all operations of Montgomery multiplication in and , input/output conversions, Mixed Radix Conversion (MRC) for integers and polynomials, dual-field modular exponentiation and inversion in the same hardware. Detailed comparisons with state-of-the-art implementations prove the potential of residue arithmetic exploitation in dual-field modular multiplication. Index Terms-Computations in finite fields, computer arithmetic, Montgomery multiplication, parallel arithmetic and logic structures.
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