Electron Injection Mechanism in Top-gate Amorphous Silicon Thin-film Transistors with Self-Aligned Silicide Source and Drain
Yifei Huang, Bahman Hekmatshoar, Sigurd Wagner, James C. Sturm
2008 Device Research Conference
The overlap between the source/drain (S/D) electrode and the gate electrode in conventional bottom-gate amorphous silicon (a-Si) thin-film transistors (TFTs), typically several µm, results in parasitic capacitance that negatively impacts the power and speed performance of a-Si circuits. Devices with S/D self-aligned to the gate do not suffer from this problem. However, self-aligned implementations of bottom-gate TFTs require lithographic exposure through the backside of the substrate, which
... nonconventional lithography tools and precludes the use of flexible substrates that are opaque in the UV range, such as metals and many plastics. Therefore, we propose, and demonstrate, a top-gate structure ( Fig. 1) , which achieves self-alignment by using the gate electrode to mask the silicide S/D formation. S/D contacts are formed directly on intrinsic a-Si (without doping) using a low-temperature (<280ºC) silicidation process that is compatible with flexible substrates . Typical DC transfer and output characteristics of a Ni silicide S/D device are shown in Fig. 2 and Fig. 3 , respectively. The devices exhibit a threshold voltage of 2.7V, saturation mobility of 1cm 2 /Vs, subthreshold slope of 600mV/dec and an ON/OFF ratio of 2x10 6 . These values are among the best ever reported for top-gate a-Si TFTs and comparable with that of the state-of-the-art bottom-gate devices. In this abstract, we examine the nature of the electron injection from the silicide contact into the channel through the lens of contact resistance (R c ). We extract R C by examining the total TFT resistance in the linear regime as a function of channel length for a range of V GS values, Fig. 4  . By extrapolating these curves to 0 channel length, we isolate the contact resistance from channel resistance at each of the V GS values (Fig. 5 ). R C is also separately and directly obtained by using a gated four-terminal device, shown in Fig. 6 , to measure the voltages at nodes inside the channel during TFT operation . The two results are in good agreement. To gain a semi-quantitative understanding of observed VGS dependence, we performed simulations to obtain the band diagram near the semiconductor surface from the silicide source to the channel (Fig. 7) . The results show significant decreases in Schottky barrier thickness and no change (to first order) in Schottky barrier height with increases in V GS . Thus we conclude that the electron injection mechanism must be tunneling. Without correcting for the effect of R C , the experimentally observed effective mobility decreases from 1cm 2 /Vs at L=100µm to 0.65 cm 2 /Vs at L=5µm while the observed effective threshold is independent channel length. This can be accurately modeled by incorporating the experimentally determined V GS -dependent R C into conventional MOSFET equations (Fig. 8) . Thus, we conclude the threshold of the device is determined by the formation of the channel and not by effect of the contact as in conventional MOSFETs. In summary, we have successfully demonstrated top-gate a-Si TFT with self-aligned nickel silicide S/D. We have shown, by examining R C , the dominant electron injection mechanism is tunneling from silicide S/D to the channel. Further, we show that the contact resistance has no influence on device threshold and little effect on effective mobility down to L=5µm.