Area-efficient instruction set synthesis for reconfigurable system-on-chip designs

Philip Brisk, Adam Kaplan, Majid Sarrafzadeh
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these compilers produce hardware that is larger than necessary, as they do not allow instructions to share hardware resources. This study presents an efficient heuristic which transforms a set of custom instructions into a single hardware datapath on which they can execute. Our approach is based on the classic problems of
more » ... nding the longest common subsequence and substring of two (or more) sequences. This heuristic produces circuits which are as much as 85.33% smaller than those synthesized by integer linear programming (ILP) approaches which do not explore resource sharing. On average, we obtained 55.41% area reduction for pipelined datapaths, and 66.92% area reduction for VLIW datapaths. Our solution is simple and effective, and can easily be integrated into an existing silicon compiler.
doi:10.1145/996566.996679 dblp:conf/dac/BriskKS04 fatcat:bvt4czqnsncudgog26zhvtm66q