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Scavenger: Automating the construction of application-optimized memory hierarchies
2015
2015 25th International Conference on Field Programmable Logic and Applications (FPL)
Abstraction • Abstraction hides implementation details and provides good programmability 2 C/Python Application Memory Processor Instruction Set Architecture CPU I/O Operating System Software Hardware programmer FPGA SRAM SRAM DRAM LUTs PCIE User Program • Implementation details are handled by programmers • Hardware can be optimized for the target application • Hardware is optimized for a set of applications and fixed at design time Abstraction • Abstraction hides implementation details and provides good programmability
doi:10.1109/fpl.2015.7294018
dblp:conf/fpl/YangFAWE15
fatcat:2qslfytbnfarvmtzg6jyfe5d4a