An 18-GHz continuous-time Σ-Δ analog-digital converter implemented in InP-transferred substrate HBT technology

S. Jaganathan, S. Krishnan, D. Mensa, T. Mathew, Y. Betser, Yun Wei, D. Scott, R. Urteaga, M. Rodwell
2001 IEEE Journal of Solid-State Circuits  
We report an 18-GHz clock-rate second-order continuous-time 6-1 analog-digital converter (ADC) implemented using InP-transferred substrate HBTs. Under two-tone test conditions, the ADC achieved 43 dB and 33 dB SNR at signal frequencies of 500 MHz and 990 MHz, respectively. The IC occupied 1.95 mm 2 die area and dissipated 1.5 W. Index Terms-ADC, delta-sigma, heterojunction bipolar transistor, substrate transfer. I. INTRODUCTION H IGH speed analog-to-digital converters (ADCs) find widespread
more » ... ications in wideband communications and radar receivers. Efforts are being made to move the ADC forward in the signal chain, closer to the antenna. Such efforts depend critically on the ability to digitize wideband signals with very high resolution. This modified architecture should result in a more robust receiver implementation consisting of the ADC followed by DSP hardware and software. A popular oversampling ADC architecture is based on -modulation. These achieve high signal/noise ratio (SNR) without requiring high precision in component values or device matching. Moreover, the requirements on the analog anti-aliasing filter are significantly relaxed. -modulators achieve high resolution by utilizing high sampling rates; a second-order ADC achieves a 15-dB improvement in SNR for every octave increase in sampling rate. The SNR of a -modulator depends on the order of the loop filter and the oversampling ratio [1] . While a high-order loop-filter results in a high SNR, it is difficult to design a stable modulator with order greater than two. High SNR can be obtained by using a second-order filter and as high an oversampling ratio as permitted by the technology of implementation. This is our approach. We seek as high a clock rate as is feasible in the technology, so as to obtain a high resolution; an ideal second-order ADC at 18-GHz clock would exhibit 10 effective Manuscript
doi:10.1109/4.944661 fatcat:m3ozfv4erbcp7l2utlyprmkwne