Dynamic Floating Output Stage for Low Power Buffer Amplifier for LCD Application

Hari Shanker Srivastava, Baghel R.K
2015 International Journal of VLSI Design & Communication Systems  
This topic proposes low-power buffer means low quiescent current buffer amplifier. A dynamic floating current node is used at the output of two-stage amplifier to increase the charging and discharging of output capacitor as well as settling time of buffer. It is designed for 10 bit digital analog converter to support for LCD column driver it is implemented in 180 nm CMOS technology with the quiescent current of 5 µA for 30 pF capacitance, the settling time calculated as 4.5µs, the slew rate
more » ... , the slew rate obtained as 5V/µs and area on chip is 30×72µ݉ ଶ .
doi:10.5121/vlsic.2015.6102 fatcat:3lyomxpbajdrtbeuvlw2hnv5ji