Application specific instruction memory transformations for power efficient, fault resilient embedded processors

R. Ayoub, P. Petrov, A. Orailoglu
IEEE International SOC Conference, 2004. Proceedings.  
In this paper we present a coding framework for a low energy instruction bur for embedded pracerras. The encoder exploits application-specific hawledge regarding program Iwl-spots to generate codewords that deliver savings in power and to funhermore provide c o n c m n t detection of ~LTOK. Power ravings can be obtained through the use of codewards h a t reduce the switching activity on the bus. The analysis shows that generating codewards that prohibit the occ~rrence of thrce consecutive
more » ... tions in h e adjacent lines is fundamental to capturing the W O K~& C~S~ crosstalk faults in the bus lines at run time, thus improving Ihe overall reliability of the bur. The desired codewords can be gencrated lhrough a set of simple prespecified transformations. The detailed analysis we outline shows that the presented transformations m optimal. The proposed encoding scheme is dymmically reprogranunable. thus targeting code panicularities effectively. The mtri~tion to a simple yet efficient set of transformations reduces the required storage capacity and eases reprogrmmlability while achieving these objectives. Extensive expaimental analysis an numerical and DSP codes indicates significant improvements in power savings. r e p~e~o f the high-lo-low -ill00 on the bw k. (I1 IO rcpsecnr either -lion evem 00 the bus line. (HI to pi sea a line ulat is steady high. and (1) to present a Lioe~hat is steady low.
doi:10.1109/socc.2004.1362405 dblp:conf/socc/AyoubPO04 fatcat:r4y4dwhdnjhnlga45xk5tvlvke