An Ultra-Low Power Expandable 4-bit Adder/Subtracter IC Using Adiabatic Dynamic CMOS Logic Circuit Technology

Kazukiyo Takahashi, Koichi Ikeda, Mitsuru Mizunuma
1999 Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials   unpublished
This paper describes a design of a 1bit Carry Propagate Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1bit CPFA/S is compared with that of the CMOS 1bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/23 as low as that of the CMOS circuits. The transistors count, propagation-delay time and energy dissipation of the ADCL 4bit CPFA/S are compared with
more » ... are compared with those of the ADCL 4bit Carry Propagate Adder/Subtracter (CPA/S). The transistors count and propagation-delay time are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1bit CPFA/S fabricated in a 1.2µm CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1MHz.
doi:10.7567/ssdm.1999.e-4-2 fatcat:tl2lnttnkbaipnu6xwqqfcf73y