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Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials
This paper describes a design of a 1bit Carry Propagate Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1bit CPFA/S is compared with that of the CMOS 1bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/23 as low as that of the CMOS circuits. The transistors count, propagation-delay time and energy dissipation of the ADCL 4bit CPFA/S are compared withdoi:10.7567/ssdm.1999.e-4-2 fatcat:tl2lnttnkbaipnu6xwqqfcf73y