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Extending SRT for parallel applications in tiled-CMP architectures
2009
2009 IEEE International Symposium on Parallel & Distributed Processing
Reliability has become a first-class consideration issue for architects along with performance and energy-efficiency. The increasing scaling technology and subsequent supply voltage reductions are increasing the susceptibility of architectures to soft errors. However, mechanisms to achieve full coverage to errors usually degrade performance in an unacceptable way for the majority of common users. Simultaneous and Redundantly Threaded (SRT) [13] is a fault tolerant architecture in which pairs of
doi:10.1109/ipdps.2009.5160902
dblp:conf/ipps/SanchezAG09
fatcat:p5rknuu5ardtjb5h4lcsdmk2ne