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A low power front-end for embedded processors using a block-aware instruction set
2007
Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '07
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since instruction fetching happens on nearly every cycle and involves accesses to large memory arrays such as instruction and branch target caches. The use of small front-end arrays leads to significant power and area savings, but typically results in significant performance degradation. This paper evaluates and compares
doi:10.1145/1289881.1289926
dblp:conf/cases/ZmilyK07
fatcat:gqhikqs4ibddbkebmgt3xeid6e