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Hardware execution throttling mechanisms such as duty cycle modulation and voltage/frequency scaling can effectively control core or chip-level resource consumption and hence have been advocated to manage multicore resource competition. However, finding the right throttle setting is challenging since the configuration space grows exponentially as the number of cores increases, making the naive approach of exhaustive search untenable. This paper proposes a flexible framework fordoi:10.1109/icpp.2012.8 dblp:conf/icpp/ZhangZDS12 fatcat:qjynudh42vefjk6r6qua7qvxta