A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2005; you can also visit the original URL.
The file type is
In this paper, we present a novel approach to the problem of clock skew minimization by buffer and wire sizing. The original nonlinear programming problem is transformed to a sequence of linear programs, by taking the first order Taylor's expansion of clock path delay with respect to buffer and wire widths. The sensitivities of clock path delay, with respect to buffer and wire widths, are efficiently updated for each linear program by applying time domain analysis to the clock network in adoi:10.1145/981066.981105 dblp:conf/ispd/WangM04 fatcat:fm3eeg52xrgydia6cahmncizuq