Clock network sizing via sequential linear programming with time-domain analysis

Kai Wang, Malgorzata Marek-Sadowska
2004 Proceedings of the 2004 international symposium on Physical design - ISPD '04  
In this paper, we present a novel approach to the problem of clock skew minimization by buffer and wire sizing. The original nonlinear programming problem is transformed to a sequence of linear programs, by taking the first order Taylor's expansion of clock path delay with respect to buffer and wire widths. The sensitivities of clock path delay, with respect to buffer and wire widths, are efficiently updated for each linear program by applying time domain analysis to the clock network in a
more » ... e-and-conquer fashion. Our technique can take into account the power supply variations, which have significant impact on clock skew. We demonstrate experimentally that in several iterations, the proposed technique is capable of reducing substantially the skew of clock networks.
doi:10.1145/981066.981105 dblp:conf/ispd/WangM04 fatcat:fm3eeg52xrgydia6cahmncizuq