SiGe digital frequency dividers with reduced residual phase noise

Stephen Horst, Stan Phillips, Hossein Lavasani, Farrokh Ayazi, John D. Cressler
2009 2009 IEEE Custom Integrated Circuits Conference  
A new design methodology for achieving very low residual phase noise in SiGe HBT digital frequency dividers is presented. A modified CML D latch design is proposed that enables the latch to draw more current, thereby reducing the residual phase noise. The latch modification yields a 10 dB phase noise improvement over a standard D latch topology, with measurements at 10 GHz resulting in a phase noise floor of -160 dBc/Hz. The circuit dissipates 350 mW of DC power, but a standard phase noise
more » ... e-of-merit that accounts for phase noise, DC power dissipation, and operating frequency, reveals that this new design is among the best in its class. IEEE 2009 Custom Intergrated Circuits Conference (CICC) 978-1-4244-4072-6/09/$25.00 ©2009 IEEE M-24-1
doi:10.1109/cicc.2009.5280851 dblp:conf/cicc/HorstPLAC09 fatcat:ethljdjdx5ewfkzpjkokgxtpae