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A new design methodology for achieving very low residual phase noise in SiGe HBT digital frequency dividers is presented. A modified CML D latch design is proposed that enables the latch to draw more current, thereby reducing the residual phase noise. The latch modification yields a 10 dB phase noise improvement over a standard D latch topology, with measurements at 10 GHz resulting in a phase noise floor of -160 dBc/Hz. The circuit dissipates 350 mW of DC power, but a standard phase noisedoi:10.1109/cicc.2009.5280851 dblp:conf/cicc/HorstPLAC09 fatcat:ethljdjdx5ewfkzpjkokgxtpae