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The conflicting yet increasing demand for high performance and low power in multi-functional chips has pushed techniques for power reduction to the forefront of VLSI design. Although recent developments have automated most of the low power implementations, designers often manually modify the circuit in order to achieve further power savings. This human intervention is often paved with many errors that are bound to typical logic functional failures. Debugging these errors can be a resourcedoi:10.1109/aspdac.2013.6509685 dblp:conf/aspdac/LeSV13 fatcat:z4hgtatyzfau5g7ol75t74fn54