A 285-MHz pipelined MAP decoder in 0.18-/spl mu/m CMOS
IEEE Journal of Solid-State Circuits
Presented in this paper is a pipelined 285-MHz maximum a posteriori probability (MAP) decoder IC. The 8.7-mm 2 IC is implemented in a 1.8-V 0.18-m CMOS technology and consumes 330 mW at maximum frequency. The MAP decoder chip features a block-interleaved pipelined architecture, which enables the pipelining of the add-compare-select kernels. Measured results indicate that a turbo decoder based on the presented MAP decoder core can achieve: 1) a decoding throughput of 27.6 Mb/s with an
... with an energy-efficiency of 2.36 nJ/b/iter; 2) the highest clock frequency compared to existing 0.18-m designs with the smallest area; and 3) comparable throughput with an area reduction of 3-4 3 with reference to a look-ahead based high-speed design (Radix-4 design), and a parallel architecture. Index Terms-CMOS, iterative processing, maximum a posteriori probability (MAP) decoder, pipeline, turbo decoder, turbo equalizer. in electrical engineering, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign (UIUC) in 2004. During the summers of 2001 and 2002, he was with the Communication Systems Laboratory, DSPS R&D Center, Texas Instruments, Inc., Dallas, TX, where he was involved in IEEE 802.11 and 802.16 modem development. Since September 2004, he has been working on DVB-H and ISDB-T modem development. His research interests include VLSI architectures for communication and signal processing systems. Authorized licensed use limited to: University of Illinois. Downloaded on July 27,2010 at 06:16:24 UTC from IEEE Xplore. Restrictions apply.