A 2-V CMOS cellular transceiver front-end

M.S.J. Steyaert, J. Janssens, B. de Muer, M. Borremans, N. Itoh
2000 IEEE Journal of Solid-State Circuits  
This work presents the design and implementation of a 2-V cellular transceiver front-end in a standard 0.25-m CMOS technology. The prototype integrates a low-IF receiver (low noise amplifier, I/Q mixers, and VGAs) and a direct-upconversion transmitter (I/Q mixers and pre-amplifier) on a single die together with a complete phase-locked loop, including a 64/79 prescaler, a fully integrated loop filter, and a quadrature voltage-controlled oscillator with on-chip inductors. Design trade-offs have
more » ... n trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low voltage. As a result, the IC operates from a power supply of only 2 V, while consuming 191 mW in receiver (RX) mode and 160 mW in transmitter (TX) mode. To build a complete transceiver system for 1.8-GHz cellular communication, only an antenna, an antenna filter, a power amplifier, and a digital baseband chip must be added to the analog front-end. This work shows the potential of achieving the analog performance required for the class I/II DCS-1800 cellular system in a standard 0.25m CMOS technology, without tuning or trimming. I. TRANSCEIVER ARCHITECTURE T HE TOPOLOGY of the implemented CMOS transceiver front-end is shown in Fig. 1 . The transceiver IC integrates a low-IF quadrature receiver, a direct upconversion transmitter, and a fully integrated phase-locked loop (PLL) synthesizer-including LC tank and loop filter-on the same CMOS die. The receive path consists of a low noise amplifier (LNA), a quadrature mixer, and an LF VGA filter. The transmit path consists of a quadrature upconversion mixer and an RF output driver. The PLL contains a fully integrated polyphase quadrature voltagecontrolled oscillator (VCO), a 64/79 modulus prescaler, a phasefrequency detector, and an on-chip loop filter with linearization. A complete 1.8-GHz cellular system ( Fig. 1) can be built by flanking the transceiver IC with an antenna filter/switch, a power amplifier, a cristal reference, and a digital baseband chip, containing the A/D, D/A, and the all-digital delta-sigma fractional-PLL steering. A low-IF/direct upconversion architecture has been selected because of its excellent integratability. Since the image rejection and the channel selection do not rely on high-filtering, in principle no external filters are required. In the receiver, the image rejection is done by quadrature down-mixing, while in the Manuscript
doi:10.1109/4.890303 fatcat:zehxbpys3zbuzo36l57pvgunt4