New spectral methods for ratio cut partitioning and clustering

L. Hagen, A.B. Kahng
1992 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Partitioning of circuit netlists is important in many phases of VLSI design, ranging from layout to testing and hardware simulation. The ratio cut objective function [29] has received much attention since it naturally captures both mincut and equipartition, the two traditional goals of partitioning. In this paper, we show that the second smallest eigenvalue of a matrix derived from the netlist gives a provably good approximation of the optimal ratio cut partition cost. We also demonstrate that
more » ... ast Lanczos-type methods for the sparse symmetric eigenvalue problem are a robust basis for computing heuristic ratio cuts based on the eigenvector of this second eigenvalue. Effective clustering methods are an immediate byproduct of the second eigenvector computation, and are very successful on the "difficult" input classes proposed in the CAD literature. Finally, we discuss the very natural intersection graph representation of the circuit netlist as a basis for partitioning, and propose a heuristic based on spectral ratio cut partitioning of the netlist intersection graph. Our partitioning heuristics were tested on industry benchmark suites, and the results compare favorably with those of Wei and Cheng [29], 1321 in terms of both solution quality and runtime. This paper concludes by describing several types of algorithmic speedups and directiops for future work. I. PRELIMINARIES S SYSTEM complexity increases, a divide-and-con-A quer approach is used to keep the circuit design process tractable. This recursive decomposition of the synthesis problem is reflected in the hierarchical organization of boards, multi-chip modules, integrated circuits, and macro cells. As we move downward in the design hierarchy, signal delays typically decrease; for example, onchip communication is faster than inter-chip communication. Therefore, the traditional metric for the decomposition is the number of signal nets which cross between layout subproblems. Minimizing this number is the essence of partitioning. Any decision made early in the layout synthesis procedure will constrain succeeding decisions, and hence good solutions to the placement, global routing, and detailed routing problems depend on the quality of the partitioning algorithm. As noted by such authors as Donath IEEE Log Number 9200832. [7] and Wei and Cheng [32], partitioning is basic to many fundamental CAD problems, including the following: Pacbging of designs: Logic is partitioned into blocks, subject to I/O bounds and constraints on block area; this is the canonical partitioning application at all levels of design, arising whenever .technology improves and existing designs must be repackaged onto higher-capacity blocks. Clustering analysis: In certain layout approaches, partitioning is used to derive a sparse, clustered netlist which is then used as the basis of constructive module placement. Partition analysis for high-level synthesis: Accurate prediction of layout area and wireability is crucial to high-level synthesis and floorplanning; predictive models rely on analysis of the partitioning structure of netlists in conjunction with output models for placement and routing algorithms. Hardware simulation and test: A good partitioning will minimize the number of inter-block signals that must be multiplexed onto a hardware simulator; similarly, reducing the number of inputs to a block often reduces the number of vectors needed to exercise the logic. A. Basic Partitioning Formulations A standard mathematical model in VLSI layout associates a graph G = (V, E) with the circuit netlist, where vertices in V represent modules, and edges in E represent signal nets. The vertices and edges of G may be weighted to reflect module area and the multiplicity or importance of a wiring connection. Because nets often have more than two pins, the netlist is more generally represented by a hypergraph H = (V, E'), where hyperedges in E' are the subsets of V contained by each net [25]. A large segment of the literature has treated graph partitioning instead of hypergraph partitioning since not only is the formulation simpler, but many algorithms are applicable only to graph inputs. In this section, we will discuss graph partitioning and defer discussion of standard hypergraph-to-graph transformations to Section 111. Two basic formulations for circuit partitioning are the following: Minimum Cut: Given G = (V, E), partition V into disjoint U and W such that e( U, W ) , i.e., the number 0277-0070/92$03.00 0 1992 IEEE
doi:10.1109/43.159993 fatcat:jostndvucnb4phxnuwucmf2wty