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The ability of a compiler to exploit loop-level parallelism in a reconfigurable array is significantly affected by the amount of flexibility in the interconnect architecture. A less flexible interconnect will make it more difficult for the compiler to find efficient loop-level pipelined schedules, leading to reduced instruction throughput, and larger configuration bit storage area. In this paper, we determine the optimum flexibility and topology for a pointto-point interconnect architecture indoi:10.1109/fpt.2004.1393248 dblp:conf/fpt/WiltonKMV04 fatcat:meoyrzbptvawtev3lgtroaskri