Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays

S.J.E. Wilton, N. Kafafi, Bingfeng Mei, S. Vernalde
Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)  
The ability of a compiler to exploit loop-level parallelism in a reconfigurable array is significantly affected by the amount of flexibility in the interconnect architecture. A less flexible interconnect will make it more difficult for the compiler to find efficient loop-level pipelined schedules, leading to reduced instruction throughput, and larger configuration bit storage area. In this paper, we determine the optimum flexibility and topology for a pointto-point interconnect architecture in
more » ... ct architecture in a reconfigurable system. We present four topologies, and show that their performance per unit area is significantly better than that that would be obtained if a fully-connected network had been used.
doi:10.1109/fpt.2004.1393248 dblp:conf/fpt/WiltonKMV04 fatcat:meoyrzbptvawtev3lgtroaskri