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Application-specific instruction set processor (ASIP) design is a promising approach for meeting the performance and cost goals of an embedded system. We have developed a new microarchitecture for automatically constructing ASIPs. This new architecture, called a wide counterflow pipeline (WCFP), is based on the counterflow pipeline (CFP). Our ASIP synthesis technique uses software pipelining and design-space exploration to generate a custom WCFP and instruction set for an embedded application.doi:10.1109/hicss.2000.926966 dblp:conf/hicss/ChildersD00 fatcat:ts7kvkmdvbeqflqpgicth6duuu