Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs

M.S. Abadir
12th IEEE International On-Line Testing Symposium (IOLTS'06)  
Extended Abstract Technology scaling has enabled electronic devices to offer much higher computational power and performance. This scaling, however, has given rise to concerns about power consumption. Power has been an important area of research in recent years. According to the International Technology Roadmap for Semiconductors (ITRS) [1], power densities (i.e. power per unit area) will soon be the limiting factor in manufacturing chips with more processing capacity. In order to reduce
more » ... tor delay times, CMOS devices were scaled down along with the supply voltage (VDD) to reduce dynamic power consumption. The transistor threshold voltage (Vth) has also been scaled down to improve performance and noise margin, which causes an increase of up to 5x in static power per generation [2] . In many cases, the static power is close to or more than 50% of the total power of the chip [3]. This situation gets much worse at operating conditions of higher temperatures.
doi:10.1109/iolts.2006.39 dblp:conf/iolts/Abadir06 fatcat:2kxfun5lmvfezf7ahptef5kcey