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This paper presents an interesting system-level co-design and co-verification case study for a non-trivial design where multiple high-performing x86 processors and custom hardware were connected through a coherent interconnection fabric. In functional verification of such a system, we used a processor bus functional model (BFM) to combine native software execution with a cycle-accurate interconnect simulator and an HDL simulator. However, we found that significant extensions need to be made todoi:10.1145/2380445.2380524 dblp:conf/codes/HongOCBKO12 fatcat:4jgtca2j6nbyrhhb2na7q2li7m