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High-performance Architecture of Network Intrusion Prevention Systems
2014
EAI Endorsed Transactions on Scalable Information Systems
Software-based Network Intrusion Prevention Systems have difficulty in handling high speed links. Network processor (NP) is an emerging field of programmable processors that are optimized to implement network data. In this paper, a novel Network Intrusion Prevention scheme is designed based on a heterogeneous multi-core processing architecture where its NP devices complement genera purpose multi-core processors to improve the performance of packet processing. We use Netronome's network
doi:10.4108/sis.1.3.e3
fatcat:wdxpm6z44ndgzb3vmslunq25b4