Mohamed H. Essai, Marina Magdy
2018 JES. Journal of Engineering Sciences  
Hardware implementation of Artificial Neural Network (ANNs) depends mainly on the efficient implementation of the activation functions. Field Programmable Gate Array is the most appropriate tool for hardware implementation of ANNs. In this paper we introduce FPGA-based hardware implementation of ANNs using five different activation functions. These implemented NNs are described using Very High Speed Integrated Circuits Hardware Description Language (VHDL) and carried out by Digilent Basys 2
more » ... tan-3E FPGA platform from Xilinx. The performances of the implemented NNs were investigated in terms of area efficient implementation, and correct prediction percentages for solving XOR, and Full-Adder problems. ANNs implementations can be categorized into: Software (SW) implementations and Hardware (HW) implementations [3]. The SW implementations offer flexibility (easy to implement), and reliability but provide poor performance. The implemented ANNs that use SW approach are simulated, trained, verified, and tested using the general purpose sequential (Von-Neuman) computers for modelling a variety of NNs. The HW implementations are generally difficult and consuming more time to be built but provide better performance in comparison with SW versions [4]. There are analog, digital and hybrid system architectures offered for the HW implementations of ANNs. Analog architectures are more accurate, but difficult to be implemented and have some of problems with weight storage. Digital architectures have the advantages of high flexibility, high accuracy, better replicability, low noise sensitivity, better testability, and weight storage does not become a problem.
doi:10.21608/jesaun.2018.110510 fatcat:blwrxlic6bfs5orvrv5gict6re