A bipartition-codec architecture to reduce power in pipelined circuits

Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Kun-Lin Tsai
2001 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper proposes a new bipatition-codec architecture that may reduce power consumption of pipelined circuits. We treat each output value of a pipelined circuit as one state of a FSM. If the output of a pipelined circuit transit mainly among few states, we could partition the combinational portion of a pipelined circuit into two blocks: one that contains the few states of high activity is small and the other that contains the remainder of low activity is big. Consequently, the state
more » ... s will be confined to the small block in most of the time. Then we replace the small block with a codec circuit, which consists of an encoder and a decoder, to reduce the internal switching activity of the block. The encoder minimizes the number of bit changes during state transitions thus the switching which propagates into decoder is reduced considerably. We present experimental results on several MCNC benchmarks and get up to 63.7% power savings by using our new architecture.
doi:10.1109/43.908477 fatcat:hmgvjeizvraerk5s5npttnzt2y